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Overview

               

To meet the ever increasing needs in floating-point arithmetic speedup of the ever higher precision and finer scale of modern computation-intensive applications, a hardware co-processor accelerator design is proposed. This paper explores the use of a double-precision floating-point multi-core scheme on a Field Programmable Gate Array (FPGA) to work in parallel with Central Processing Unit (CPU). The shared-memory system architecture chosen will allow high-speed queuing of operations to be performed on the FPGA in a parallel manner. To avoid memory contention, this system requires a high-speed bus controller as well as an on-chip internal floating-point core parallelization bus controller. In the current design, this multi-core FPGA chip replaces one of the on-board dual AMD Opteron PEs (Processing Elements) in DRC system. A fault-tolerant safe guard is also added with duplicated computation plus voting.