CENG 6332: High Performance Computer Architecture

Fall 2016

UHCL Computer Engineering

Description

Introduction to systems architecture design and tuning techniques for High Performance Computing; RISC’s, cache, pipelines, hypercubes, data-flow and supercomputers.

Instructor

Dr. Hakduran Koc

Room : Delta 110

Email : KocHakduran at uhcl dot edu

Web : http://sceweb.sce.uhcl.edu/koch/

Phone : x3877

Office Hours: Mon 12-2pm, Wed 12-1pm, Thu 1-3pm

Teaching Assistant

Pranitha Madupu

Room : D132

Email : MadupuP5270 at uhcl dot edu

Office Hours: Mon 4-7pm, Tue 12-5pm, Wed 1pm-4pm, Thu 4pm-7pm

Meeting

Tue 1:00-3:50pm in Room D234

Textbook

Parallel Computer Organization and Design by Michel Dubois, Murali Annavaran, and Per Stenstrom; 1^st Edition, Cambridge University Press, 2012, ISBN: 9780521886758.

References

Computer Architecture: A Quantitative Approach by John Hennessy and David Patterson; 5th Edition; Morgan Kaufmann; 20011; ISBN: 9780123838728.

Tentative Course Schedule

Date	Topics covered
Aug. 23	Intro to class, Overview, Syllabus
Aug. 30	Ch. 1 – Introduction HW 1 – Due: September 20
Sept. 6	Performance Analysis HW 2 – Due: September 27 Ch. 2 – Impact of Technology
Sept. 13	Ch. 3 - Processor Microarchitecture
Sept. 20	Processor and Pipelining Ch. 3 - Processor Microarchitecture (cont.)
Sept. 27	Ch. 3 - Processor Microarchitecture (cont.) HW 3 – Due: ??? HW 4 – Due: ???
Oct. 4	Ch. 3 - Processor Microarchitecture (cont.)
Oct. 11	Ch. 4 - Memory Hierarchies Memory Hierarchy Basics and Design
Oct. 18	Exam 1 – October 18 (tentative) Sample Exam
Oct. 25	Ch. 4 - Memory Hierarchies (cont.) HW 5 – Due: ???
Nov. 1	Ch. 4 - Memory Hierarchies (cont.) HW 6 – Due: ???
Nov. 8	Ch. 5 - Multiprocessor Systems
Nov. 15	Ch. 6 - Interconnection Networks
Nov. 22	Ch. 7 - Coherence, Synchronization, and Memory Consistency
Nov. 29	Ch. 8 - Chip Multiprocessors
	Exam 2 - December 3 (tentative)
Grades - (Updated: --) Section 1

LINKS

- Top500

- SPEC Benchmarks

CENG 6332