CENG 6332: High Performance Computer Architecture

Fall 2014

UHCL Computer Engineering

Description

Introduction to systems architecture design and tuning techniques for High Performance Computing; RISC’s, cache, pipelines, hypercubes, data-flow and supercomputers.

Instructor

Dr. Hakduran Koc

Room  : Delta 110

Email  : KocHakduran at uhcl dot edu

Web    : http://sceweb.sce.uhcl.edu/koch/

Phone : x3877

Office Hours: Tue 2-4pm, Thu 2-4pm

Teaching Assistant

TA 1: Elham Azari

Room  : D132

Email  : AzariE8517 at uhcl dot edu

Office Hours: Wed 10am-5pm, Thu 10am-5pm

TA 2: Oommen Mathews

Room  : D132

Email  : MathewsO9565 at uhcl dot edu

Office Hours: Mon 9am-5pm, Tue 9am-3pm

Meeting

Section 1: Wed 1:00-3:50pm in Room D136

Section 2: Wed 4:00-6:50pm in Room D242

Textbook

Parallel Computer Organization and Design by Michel Dubois, Murali Annavaran, and Per Stenstrom; 1st Edition, Cambridge University Press, 2012, ISBN: 9780521886758.

References

Computer Organization and Design: The Hardware and Software Interface by David Patterson and John Hennessy, Revised 4th Edition, Morgan Kaufmann, 2011; ISBN: 9780123747501.

Computer Architecture: A Quantitative Approach by John Hennessy and David Patterson; 5th Edition; Morgan Kaufmann; 20011; ISBN: 9780123838728.

Tentative Course Schedule

Date

Topics covered

Aug. 27

Intro to class, Overview, Syllabus

Sept. 3

Ch. 1 – Introduction                                              

HW 1 – Due: September 24

Sept. 10

Performance Analysis

HW 2 – Due: October 1

Ch. 2 – Impact of Technology

Sept. 17

Ch. 3 - Processor Microarchitecture

Sept. 24

Processor and Pipelining

Ch. 3 - Processor Microarchitecture (cont.)

Oct. 1

Ch. 3 - Processor Microarchitecture (cont.)

HW 3 – Due: October 15

Oct. 8

Ch. 3 - Processor Microarchitecture (cont.)

Oct. 15

Ch. 4 - Memory Hierarchies

Memory Hierarchy Basics and Design

HW 4 – Due: October 26

Oct. 22

Exam 1 is on Oct. 26 at 1pm in D241 (No class on Oct. 22)

Sample Exam

Oct. 29

Ch. 4 - Memory Hierarchies (cont.)

HW 5 – Due: November 5

Ch. 5 - Multiprocessor Systems

Nov. 5

Ch. 5 - Multiprocessor Systems (cont.)

HW 6 – Due: November 19

Nov. 12

Ch. 6 - Interconnection Networks

Nov. 19

Ch. 7 - Coherence, Synchronization, and Memory Consistency

Nov. 26

Thanksgiving Holiday (November 26-28)

Dec. 3

Ch. 8 - Chip Multiprocessors

Dec. 7

Exam 2 is on Sunday, Dec. 7 in Room 241

Grades - (Updated: October 15)

   Section 1

   Section 2

LINKS

- Tom’s Hardware

- Top500

- SPEC Benchmarks

 

CENG 6332