CENG 5534 - Advanced Digital System Design

Summer 2015

UHCL Computer Engineering

Description

Behavioral and structural design methods and examples using hardware description languages (VHDL & Verilog).  Control, arithmetic, bus systems, memory systems.  Logic synthesis from hardware language descriptions.

Instructor

Dr. Hakduran Koc

Room : D110

Email : KocHakduran at uhcl dot edu

Phone : x3877

Office Hours: tba

Teaching Assistant

Hoang Nguyen

Room : D132

Email : NguyenH0798 at uhcl dot edu

Office Hours: Mon 1pm-3pm & 6pm-9pm, Wed 1pm-3pm & 6pm-9pm, Thu 12:45pm-4:45pm

Meeting

Section 11: Mon & Wed 12:00pm-2:50pm at D119A

Section 12: Tue & Thu 12:00pm-2:50pm at D136

Textbook

Circuit Design and Simulation with VHDL by Volnei A. Pedroni, MIT Press, 2nd edition, 2010. ISBN: 9780262014335.

References

- The Designer's Guide to VHDL by Peter Ashenden, Morgan Kaufmann, 3rd Edition, 2008. ISBN: 9780120887859.

- Fundamentals of Logic Design by Charles H. Roth, Jr. and Larry L. Kinney, Cengage Learning, 6th Edition, 20010. ISBN: 9780495471691.

Tentative Course Schedule

Date

Topics covered

June 8-10

Introduction, Syllabus, Laboratory

Objectives

Design Methodology and Alternatives

HW 1 Due: June 17-Section 11; June 18-Section 12

June 15-17

VHDL Basics and Sample Codes

Combinational Logic, Sample Codes

HW 2 Due: June 24-Section 11; June 25-Section 12

June 22-24

Sequential Logic, State Machine Design

Modeling for simulation

HW 3 Due: July 1-Section 11; July 2-Section 12

June 29- July 1

Derivation of State Graphs and Tables

Analysis of Sequential Circuits

HW 4 Due: July 8-Section 11; July 9-Section 12

Exam 1

Sample Exam - 1

Sample Exam - 2

Sample Exam - 3

July 6-8

Reduction of State Tables and State Assignments

Sequential Circuit Design

Sequential Circuit Optimizations

HW 5 Due: July 15-Section 11; July 16-Section 12

July 13-15

State Machines in VHDL

Controller Design Examples and VHDL Implementations

Circuits for Arithmetic Operations

VHDL for Digital System Design

HW 6 Due: July 22-Section 11; July 23-Section 12

Final Project Due: July 29 for both sections

July 20-22

Hierarchical Design CPU, ALU example

VHDL Synthesis Style and Performance Guidelines

July 27-29

Review, Exam 2

Project Demo

Grades (Updated: --/--)

Links

- Xilinx ISE WebPACK: You may install it in your PC (Registration is free of charge).

- Documents from Xilinx website:

- Xilinx ISE Software Manuals

- Xilinx ISE Qiuck Start Tutorial

- Xilinx ISE In-Dept Tutorial

- Xilinx ISE Simulation and Synthesis Design Guide

 

- Xilinx ISE Tutorial for Version 14.4!

 

- FPGA Tutorial

CENG 5534