CENG 5534 - Advanced Digital System Design

Spring 2014

UHCL Computer Engineering

Description

Behavioral and structural design methods and examples using hardware description languages (VHDL & Verilog).  Control, arithmetic, bus systems, memory systems.  Logic synthesis from hardware language descriptions.

Instructor

Dr. Hakduran Koc

Room : D110

Email : KocHakduran at uhcl dot edu

Phone : x3877

Office Hours: Tue 12pm-3pm, Thu 12pm-3pm

Teaching Assistant

Oommen Mathews

Room : PC Lab (Delta Second Floor)

Email : MathewsO9565 at uhcl dot edu

Office Hours: Mon 8:30am 2:30pm, Tue 8:30am 2:30pm, Wed 8:30 10:30am

Meeting

Wed 1:00pm-3:50pm at D136

Textbook

Circuit Design and Simulation with VHDL by Volnei A. Pedroni, MIT Press, 2nd edition, 2010. ISBN: 9780262014335.

References

- The Designer's Guide to VHDL by Peter Ashenden, Morgan Kaufmann, 3rd Edition, 2008. ISBN: 9780120887859.

- Fundamentals of Logic Design by Charles H. Roth, Jr. and Larry L. Kinney, Cengage Learning, 6th Edition, 20010. ISBN: 9780495471691.

Announcements

 

- Welcome to CENG 5534!

 

Tentative Course Schedule

Date

Topics covered

Jan. 15

Introduction, Syllabus, Laboratory

Objectives

Jan. 22

Design Methodology and Alternatives

HW 1 Due: February 5

Jan. 29

VHDL Basics and Sample Codes

HW 2 Due: February 12

Feb. 5

Combinational Logic, Sample Codes

HW 3 Due: February 19

Feb. 12

Sequential Logic, State Machine Design

HW 4 Due: February 26

Feb. 19

Modeling for simulation

HW 5 Due: March 19

Feb. 26

Derivation of State Graphs and Tables

Analysis of Sequential Circuits

HW 6 Due: March 26

Sample Exam - 1

Sample Exam - 2

Mar. 5

Review

Exam 1

Mar. 12

Spring Break

Mar. 19

Reduction of State Tables and State Assignments

HW 7 Due: April 2 (BONUS ASSIGNMENT)

Mar. 26

Sequential Circuit Design

Sequential Circuit Optimizations

HW 8 Due: April 9

Apr. 2

State Machines in VHDL

Final Project Due: April 23

Apr. 9

Controller Design Examples and

VHDL Implementations

Circuits for Arithmetic Operations

VHDL for Digital System Design

Apr. 16

Hierarchical Design CPU, ALU example

VHDL Synthesis Style and Performance Guidelines

Optimizations Examples

Apr. 23

Future trends, Review, Final Project Demo

Final Exam April 30 (Tentative)

Grades (Updated: April 9)

Links

- Xilinx ISE WebPACK: You may install it in your PC (Registration is free of charge).

- Documents from Xilinx website:

- Xilinx ISE Software Manuals

- Xilinx ISE Qiuck Start Tutorial

- Xilinx ISE In-Dept Tutorial

- Xilinx ISE Simulation and Synthesis Design Guide

 

- Xilinx ISE Tutorial for Version 14.4!

 

- FPGA Tutorial

CENG 5534