CENG 5534 - Advanced Digital System Design

Summer 2014

UHCL Computer Engineering

Description

Behavioral and structural design methods and examples using hardware description languages (VHDL & Verilog).  Control, arithmetic, bus systems, memory systems.  Logic synthesis from hardware language descriptions.

Instructor

Dr. Hakduran Koc

Room    : D110

Email    : KocHakduran at uhcl dot edu

Phone   : x3877

Hours    : Tue 2-4pm

Teaching Assistant

Seyit Ozturk

Email    : OzturkS0642 at uhcl dot edu

Room    : D132

Hours    : Mon: 5-6pm, Tue: 5-9pm, Wed: 5-6pm, Thu: 5-9pm, Fri: 5-9pm

Mehmet Ucar

Email    : UcarM3159 at uhcl dot edu

Room    : D132

Hours    : Mon: 4-6pm, Tue: 4-6pm, Wed: 4-6pm, Thu: 4-6pm & 8:30-10:30pm, Fri: 5-9pm

Meeting

Section 1: Mon & Wed 3pm-5:29pm at D136

Section 3: Mon & Wed 12pm-2:29pm at D136

Textbook

Circuit Design and Simulation with VHDL by Volnei A. Pedroni, MIT Press, 2nd edition, 2010. ISBN: 9780262014335.

References

- The Designer's Guide to VHDL by Peter Ashenden, Morgan Kaufmann, 3rd Edition, 2008. ISBN: 9780120887859.

- Fundamentals of Logic Design by Charles H. Roth, Jr. and Larry L. Kinney, Cengage Learning, 6th Edition, 2010. ISBN: 9780495471691.

Tentative Course Schedule

Date

Topics covered

June 2–4

Introduction, Syllabus, Objectives, Laboratory

Design Methodology and Alternatives

HW 1 – Due: June 11

June 9–11

VHDL Basics and Sample Codes

Combinational Logic, Sample Codes

HW 2 – Due: June 18

June 16–18

Sequential Logic

Modeling for simulation

HW 3 – Due: June 25

June 23–25

Derivation of State Graphs and Tables

Analysis of Sequential Circuits

HW 4 – Due: July 2

HW 5 – Due: July 9

June 30–July 2

Review

Exam 1

Sample Exam - 1

Sample Exam - 2

July 7-9

Reduction of State Tables and State Assignments

Sequential Circuit Design

HW 6 – Due: July 21 (BONUS ASSIGNMENT)

July 14-16

State Machines in VHDL

Circuits for Arithmetic Operations

VHDL for Digital System Design

Final Project – Due: July 28

July 21-23

Hierarchical Design – CPU, ALU example

Future trends, Review

July 28-30

Final Project Demo

Final Exam – July 30 (Tentative)

Links

 

- Grades: Section 1 & Section 3 (Updated: July 22)

 

- Xilinx ISE WebPACK: You may install it in your PC (Registration is free of charge).

- Documents from Xilinx website:

            - Xilinx ISE Software Manuals

            - Xilinx ISE Qiuck Start Tutorial

            - Xilinx ISE In-Dept Tutorial

            - Xilinx ISE Simulation and Synthesis Design Guide

- Xilinx ISE Tutorial – for Version 14.4

- FPGA Tutorial

 

CENG 5534